1. Field of the Invention
The present invention relates to dielectric materials used in semiconductor integrated circuits. More particularly, the present invention relates to improvements in the mechanical strength of low-k layers used as dielectric layers in semiconductor integrated circuits.
2. Description of the Related Art
As integrated circuits become smaller, it becomes more desirable to reduce interconnection delays through the selection of materials used in the interconnects and associated dielectric layers. The propagation delays through the interconnects are proportional to the resistance of the interconnects and the capacitance offered by the dielectric. In fact, as integrated devices become smaller, the RC-delay time of signal propagation along interconnects becomes the dominant factor limiting overall chip speed.
For conductors, copper has gained favor in the industry because of its many advantages, including its low resistance. In such processes, conducting metal (e.g., copper) is inlaid into trench and via structures of insulating material (e.g., low-K dielectric materials). CMP (Chemical Mechanical Polishing) is used to remove conducting metal (e.g., copper) in single or dual damascene processes. With the advent of copper technology, R has been minimized and attention has been focused on reducing C.
One way of reducing capacitance is to reduce the average dielectric constant k of the thin insulating films surrounding interconnects through the introduction of porosity. The dielectric layers in conventional integrated circuits have traditionally been formed of SiO2, which has a dielectric constant of about 4.0. A number of dielectric materials have been developed having a dielectric constant lower than that of SiO2. These are generally referred to as low-k materials.
But low-k materials used in interconnect dielectrics exhibit low mechanical strength. That is, the lack of mechanical rigidity of the composite low-k and metal interconnect materials causes delamination of the low-k to low-k layers when shear forces are applied. The mechanical strength of low-k films has been reported to be 5 times less than that of traditional silicon dioxide. Integrated circuits are often made up of thousands of active devices formed in or on silicon substrates. The active devices are interconnected to form functional circuits and components through the use of well-known multilevel interconnections. Interconnection structures normally have a first layer of metallization, an interconnection layer, a second level of metallization, and sometimes a third or other subsequent levels of metallization. The low-k dielectric materials are used to electrically isolate the different levels of metallization in a silicon substrate or well. The electrical connections between different interconnection levels are made through the use of metallized vias. Thus, a semiconductor device may include several low-k layers attached on top of each other, each low-k layer to low-k layer interface offering a potential delamination problem.
Moreover, low-k materials offer poor resistance to compression. This is significant in packaging of dies. For example, once the integrated circuits on the wafer are completed, i.e., layering and patterning are implemented, the wafer is conventionally sliced into sections known as die. The die are conventionally packaged to facilitate electrical connections to external circuitry. Generally, in semiconductor manufacturing, an individual semiconductor die is mounted to a substrate and then sealed by an encapsulant or by a molding operation. After mounting, electrical connection from the die to the package bonding pads may be completed using wire bonding techniques, for example. Typically, after packaging, the packaged die is placed flat on the printed circuit board (“PCB”) and electrical connections made to traces or landings on the printed circuit board, for example by wire bonding, solder ball bonding, or other conventional methods.
Any of these connection methods may place large stress forces on the substrate. For example, wire bonding requires that a large compressive force be placed on the bonding pad as heat is generated to “weld” the bonding wire to the pad. In using solder balls for connections to external circuitry, the ball bonding process window is directly related to the mechanical strength of the composite films that make up the bed and affects the ability to route circuitry under the ball bond pad. Often, however, the low-k layers underneath the bonding pad may comprise as may as 10 or more layers. The poor mechanical strength of the low-k material under the bonding pad thus may affect the ability to route circuitry under the ball bond pad. That is, interconnect circuitry placed under the bond pad may be damaged from the forces imposed during wire bonding, such as by crushing the underlying dielectric layers, or similarly damaged from other electrical connection methods. The poor mechanical properties of the low k film affect the overall reliability of the chip and the types of packages that can be used for the chip.
Accordingly, it is desirable to provide improved mechanical strength in low-k dielectric layers used in semiconductor devices so that greater flexibility may be achieved in locating bonding pads and forming electrical connections over the low-k dielectric layers and in order to form dies having greater strength.